A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-μm CMOS standard cell library, and which achieves over 10-Gbps throughput in all encryption modes, including cipher block chaining (CBC) mode. Although the CBC mode is the most widely used and important, achieving su...
| Published in: | IEEE Transactions on VLSI systems 12, 7 (2004). |
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| Main Author: | |
| Format: | Article |
| Language: | English |
| Subjects: |