APA aipamena

Morioka, S. A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Transactions on VLSI systems.

Chicago Style aipamena

Morioka, S. "A 10-Gbps Full-AES Crypto Design with a Twisted BDD S-Box Architecture." IEEE Transactions on VLSI Systems .

MLA aipamena

Morioka, S. "A 10-Gbps Full-AES Crypto Design with a Twisted BDD S-Box Architecture." IEEE Transactions on VLSI Systems, .