Robust interfaces for mixed-timing systems.

This paper presents several low-latency mixed-timing FIFO (first-in-first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are then adapted to work between systems with very long interco...

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Xuất bản năm:	IEEE Transactions on VLSI systems 12, 8 (2004).
Tác giả chính:	Chelcea, T.
Định dạng:	Bài viết
Ngôn ngữ:	English
Những chủ đề:	Asynchronous system. Interconnect delays. Interface operating speeds. Interface systems on chip. Latency insensitive protocols. Low latency mixed timing first-in-first-out interfaces. Low-latency mixed-timing FIFO interfaces designs. Metastability. Mixed timing domains. Mixed-timing systems. Robust interfaces. Single clock solution. Synchronous system.