Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.

Most microprocessors employ the on-chip caches to bridge the performance gap between the processor and the main memory. However, the cache accesses usually contribute significantly to the total power consumption of the chip. Based on the observation that an overwhelming majority of the values writte...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:IEEE Transactions on VLSI systems 12, 8 (2004).
1. autor: Yen-Jen Chang
Format: Artykuł
Język:English
Hasła przedmiotowe:
MediaBench traces.
SPEC2000.
Architecture level.
Asymmetric inverter pair.
Baseline instruction.
Cache power consumption minimisation.
Cache power reduction.
Circuit level method.
Data caches.
High write zero rate.
Microprocessors.
On-chip caches.
Power consumption.
Software independence.
Zero-aware asymmetric SRAM cell.