High-speed VLSI architectures for the AES algorithm.

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combi...

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Detaylı Bibliyografya
Yayımlandı:IEEE Transactions on VLSI systems 12, 9 (2004).
Yazar: Xinmiao Zhang
Materyal Türü: Makale
Dil:English
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