High-speed VLSI architectures for the AES algorithm.

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combi...

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Pubblicato in:	IEEE Transactions on VLSI systems 12, 9 (2004).
Autore principale:	Xinmiao Zhang
Natura:	Articolo
Lingua:	English
Soggetti:	FPGA implementation. Xilinx XCV1000 e-8 bg560 device. Advanced encryption standard algorithm. Combinational logic design. Composite field arithmetic. Hardware implementation. High-speed VLSI architectures. High-speed architectures. Invsubbytes transformations. Key expansion architecture. Look-up tables. Nonfeedback modes. Subbytes transformations. Subpipelining.