APA引文

Chua-Chin Wang. A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. IEEE Transactions on VLSI systems.

芝加哥风格引文

Chua-Chin Wang. "A 4-kB 500-MHz 4-T CMOS SRAM Using Low-VTHN Bitline Drivers and High-VTHP Latches." IEEE Transactions on VLSI Systems .

MLA引文

Chua-Chin Wang. "A 4-kB 500-MHz 4-T CMOS SRAM Using Low-VTHN Bitline Drivers and High-VTHP Latches." IEEE Transactions on VLSI Systems, .