Highly efficient, limited range multipliers for LUT-based FPGA architectures. - Turner, R.H.
A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area reductions of 31%-70% and speed increases of 5%-35% when compared to designs using general-purpose multipliers. The technique gives superior results over other fixed coefficient methods and is applicable to a range of FPGA technologies.
Keywords: FPGA architectures; Xilinx Virtex field programmable gate array; Discrete cosine transform; Limited range multipliers; Look up table; Poly phase filter