Highly efficient, limited range multipliers for LUT-based FPGA architectures.

Highly efficient, limited range multipliers for LUT-based FPGA architectures.

A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area r...

Descrizione completa

Dettagli Bibliografici
Pubblicato in:IEEE Transactions on VLSI systems 12, 10 (2004).
Autore principale: Turner, R.H
Natura: Articolo
Lingua:English
Soggetti:
FPGA architectures.
Xilinx Virtex field programmable gate array.
Discrete cosine transform.
Limited range multipliers.
Look up table.
Poly phase filter.