Design of FPGA interconnect for multilevel metallization. - DeHon, A.
How does multilevel metallization impact the design of field-programmable gate arrays (FPGA) interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's mesh-of-trees (MoT), which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area; this is in stark contrast to traditional, Manhattan FPGA routing schemes where switching requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto "FPGA Place and Route Challenge," arity-4 MoT networks require 26% fewer switches than the standard, Manhattan FPGA routing scheme.
Keywords: FPGA interconnection; FPGA place and route challenge; FPGA wiring schemes; Leighton mesh-of-trees.; Manhattan FPGA routing scheme; Arbitrary device scaling; Arity-4 mesh-of-tree networks; Field programmable gate arrays; Metal layers; Multilevel metallization; Network size; Topology