00000cab a22000003a 4500 UP-99796217609611810 Buklod 20231007234427.0 m |o d | ta 110114s xx d | ||r ||||| || DENGII eng Blotti, A. Ultralow-power adiabatic circuit semi-custom design. pp. 1248-1253 This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-μm CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3÷6) even when the losses in power-clock generation are considered. 0.6 micron. 10 MHz. 100 MHz. CMOS technology. VLSI designer. Carry lookahead adders. Complex adiabatic systems. Energy reduction. Energy saving. Parallel multipliers. Positive feedback adiabatic logic. Post layout simulations. Power clock generation. Semicustom adiabatic arithmetic units. Semicustom design. Static CMOS implementation. Ultralow power adiabatic circuit design. IEEE Transactions on VLSI systems 12, 11 (2004). FO UPD DENG-II Article