Lowering power consumption in concurrent checkers via input ordering.

Lowering power consumption in concurrent checkers via input ordering.

This paper presents an efficient and scalable technique for lowering power consumption in checkers used for concurrent error detection. The basic idea is to exploit the functional symmetry of concurrent checkers with respect to their inputs, and to order the inputs such that switching activity (and...

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Publicat a:IEEE Transactions on VLSI systems 12, 11 (2004).
Autor principal: Mohanram, K.
Format: Article
Idioma:English
Matèries:
Checker minimisation.
Circuit complexity.
Computational costs.
Concurrent checkers.
Concurrent error detection.
Cost function reduction.
Function logic.
Functional symmetry.
Input ordering.
Logic spatial correlations.
Optimization problem.
Power consumption reduction.
Probability.
Switching activity.