Mohanram, K. Lowering power consumption in concurrent checkers via input ordering. IEEE Transactions on VLSI systems.
Cita Chicago (17th ed.)Mohanram, K. "Lowering Power Consumption in Concurrent Checkers via Input Ordering." IEEE Transactions on VLSI Systems .
Cita MLA (9th ed.)Mohanram, K. "Lowering Power Consumption in Concurrent Checkers via Input Ordering." IEEE Transactions on VLSI Systems, .
Atenció: Aquestes cites poden no estar 100% correctes.