00000cab a22000003a 4500 UP-99796217609611803 Buklod 20231007234427.0 m |o d | ta 110114s xx d | ||r ||||| || DENGII eng Yuh-Fang Tsai Characterization and modeling of run-time techniques for leakage power reduction. pp. 1221-1233 While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and compare three techniques: input vector control, body bias control, and power supply gating. We determine their limits and benefits in terms of the potential leakage reduction, performance penalty, and area and power overhead. The leakage power savings trends considering technology scaling are also presented. Due to the differences in the properties of datapath logic and memory structures, different implementations are recommended. Finally, the use of the "minimum idle time" parameter, as a metric for evaluating different leakage control mechanisms, is shown. Body bias control. Circuit level optimization. Datapath logic. Input vector control. Leakage control mechanisms. Leakage power reduction. Memory structures. Potential leakage reduction. Power supply gating. Run time technique modeling. IEEE Transactions on VLSI systems 12, 11 (2004). FO UPD DENG-II Article