Characterization and modeling of run-time techniques for leakage power reduction.

Characterization and modeling of run-time techniques for leakage power reduction.

While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and compare three techniques: input vector control, body bias control, and power supply gating....

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Pubblicato in:IEEE Transactions on VLSI systems 12, 11 (2004).
Autore principale: Yuh-Fang Tsai
Natura: Articolo
Lingua:English
Soggetti:
Body bias control.
Circuit level optimization.
Datapath logic.
Input vector control.
Leakage control mechanisms.
Leakage power reduction.
Memory structures.
Potential leakage reduction.
Power supply gating.
Run time technique modeling.