Characterization and modeling of run-time techniques for leakage power reduction.

Characterization and modeling of run-time techniques for leakage power reduction.

While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and compare three techniques: input vector control, body bias control, and power supply gating....

Ausführliche Beschreibung

Bibliographische Detailangaben
Veröffentlicht in:IEEE Transactions on VLSI systems 12, 11 (2004).
1. Verfasser: Yuh-Fang Tsai
Format: Artikel
Sprache:English
Schlagworte:
Body bias control.
Circuit level optimization.
Datapath logic.
Input vector control.
Leakage control mechanisms.
Leakage power reduction.
Memory structures.
Potential leakage reduction.
Power supply gating.
Run time technique modeling.