Yuh-Fang Tsai. Characterization and modeling of run-time techniques for leakage power reduction. IEEE Transactions on VLSI systems.
Citace podle Chicago (17th ed.)Yuh-Fang Tsai. "Characterization and Modeling of Run-time Techniques for Leakage Power Reduction." IEEE Transactions on VLSI Systems .
Citace podle MLA (9th ed.)Yuh-Fang Tsai. "Characterization and Modeling of Run-time Techniques for Leakage Power Reduction." IEEE Transactions on VLSI Systems, .
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