Hong-Yi Huang. Interconnect accelerating techniques for sub-100-nm gigascale systems. IEEE Transactions on VLSI systems.
Chicago Style (17th ed.) CitationHong-Yi Huang. "Interconnect Accelerating Techniques for Sub-100-nm Gigascale Systems." IEEE Transactions on VLSI Systems .
MLA (9th ed.) CitationHong-Yi Huang. "Interconnect Accelerating Techniques for Sub-100-nm Gigascale Systems." IEEE Transactions on VLSI Systems, .
Warning: These citations may not always be 100% accurate.