Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors.
In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density...
| Cyhoeddwyd yn: | IEEE Transactions on VLSI systems 12, 11 (2004). |
|---|---|
| Prif Awdur: | |
| Fformat: | Erthygl |
| Iaith: | English |
| Pynciau: |