A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications.
A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8× to 10× of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in...
| প্রকাশিত: | IEEE Transactions on VLSI systems 12, 12 (2004). |
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| প্রধান লেখক: | |
| বিন্যাস: | প্রবন্ধ |
| ভাষা: | English |
| বিষয়গুলি: |