A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications.

A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8× to 10× of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in...

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发表在:	IEEE Transactions on VLSI systems 12, 12 (2004).
主要作者:	Chua-Chin Wang
格式:	文件
语言:	English
主题:	Delayed lock loop. Power dissipation. Programmable DLL based frequency multiplier. Voltage controlled delay tap line. Wireless applications. 1.2 GHz. 100 to 150 MHz. 2.5 V. 52.5 mW. CMOS local oscillator. TSMC 1P5M CMOS process.