Routability checking for three-dimensional architectures. - Hung, W.N.N.
We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. The method can incrementally incorporate additional constraints driven by timing, performance, and design. We used the latest satisfiability solver to validate the effectiveness of our approach. The experimental results demonstrate the encouraging performance on difficult routing benchmarks.
Keywords: ASIC; Boolean constraints; Circuit layout CAD; Field programmable gate arrays; Graph theory; Multichip modules; Network routing; Reconfigurable computing architectures; Routability; Satisfiability; Three dimensional architectures; Three dimensional interconnect layout