Routability checking for three-dimensional architectures.

We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. T...

詳細記述

書誌詳細

出版年:	IEEE Transactions on VLSI systems 12, 12 (2004).
第一著者:	Hung, W.N.N
フォーマット:	論文
言語:	English
主題:	ASIC. Boolean constraints. Circuit layout CAD. Field programmable gate arrays. Graph theory. Multichip modules. Network routing. Reconfigurable computing architectures. Routability. Satisfiability. Three dimensional architectures. Three dimensional interconnect layout.