Routability checking for three-dimensional architectures.

Routability checking for three-dimensional architectures.

We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. T...

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Vydáno v:IEEE Transactions on VLSI systems 12, 12 (2004).
Hlavní autor: Hung, W.N.N
Médium: Článek
Jazyk:English
Témata:
ASIC.
Boolean constraints.
Circuit layout CAD.
Field programmable gate arrays.
Graph theory.
Multichip modules.
Network routing.
Reconfigurable computing architectures.
Routability.
Satisfiability.
Three dimensional architectures.
Three dimensional interconnect layout.