SOC test planning using virtual test access architectures.

SOC test planning using virtual test access architectures.

Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to gigahertz speeds. However, system-on-chip (SOC) scan chains are typically run at lower frequencies, e.g., 10-50 MHz. The use of high-speed ATE channels to drive slower scan chains leads to an un...

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Bibliografiske detaljer
Udgivet i:IEEE Transactions on VLSI systems 12, 12 (2004).
Hovedforfatter: Sehgal, A.
Format: Article
Sprog:English
Fag:
ITC'02 SOC test benchmarks.
Lagrange multipliers.
SOC test planning.
SOC test power consumption.
Automatic test equipment.
High speed ATE channels.
System on chip scan chains.
Test access mechanism optimization.
Test cost reduction.
Tester technology.
Testing time reduction.
Virtual test access architectures.