TY  - JOUR
T1  - Synchronization overhead in SOC compressed test.
JF  - IEEE Transactions on VLSI systems
A1  - Gonciari, P.T
LA  - English
UL  - https://tuklas.up.edu.ph/Record/UP-99796217609611634
AB  - Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-chip. This paper analyzes the sources of synchronization overhead and discusses the different tradeoffs, such as area overhead, test time and automatic test equipment extensions. A novel scalable and programmable on-chip distribution architecture is proposed, which addresses the synchronization overhead problem and facilitates the use of low cost testers for manufacturing test. The design of the proposed architecture is introduced in a generic framework, and the implementation issues (including the test controller and test set preparation) have been considered for a particular case.
KW  - ATE.
KW  - SOC compressed test.
KW  - Automated test equipment.
KW  - Core based systems-on-chip.
KW  - Decoders.
KW  - Integrated circuit testing.
KW  - Programmable on-chip distribution architecture.
KW  - Scalable on-chip distribution architecture.
KW  - Synchronization overhead.
KW  - System under test.
KW  - Test controller.
KW  - Test data compression.
KW  - Test set preparation.
ER  -