Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers. - Lok-Kee Ting
High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.
Keywords: 120 MHz; DLMS algorithm; LMS recursive system; Adaptive least mean square filter; Delayed LMS algorithm; Direct form; Electronic support measures digital receivers; Fine-grained pipelining; High speed field programmable gate array implementation; High-speed Virtix FPGA implementation; Output latency; Pipelined adaptive LMS predictor; Processor; Sampling rate; Transposed form