00000cab a22000003a 4500 UP-99796217609611611 Buklod 20231007234428.0 m |o d | ta 110113s xx d | ||r ||||| || DENGII eng Yiran Chen Current demand balancing a technique for minimization of current surge in high performance clock-gated microprocessors. pp. 75-85 We propose an integrated architectural and physical planning approach to minimize the current surge in high-performance clock-gated microprocessors. In our approach, we use priority assignment optimization (PAO) and dynamic functional unit (FU) selection (DFS) to balance current demand in the floorplan. Two complementary methods-FU ordering with submodule design and issue pattern management-are also proposed to enhance the above techniques. Experimental results show that at the 0.18-μm technology node, the PAO can reduce the peak noise by 11.75% and consequently, the decoupling capacitance (Decap) requirement by 24.22% without any degradation in instructions per cycle (IPC). Moreover, an enhanced DFS reduces the peak noise by 13.39% as well as Decap requirement by 29.58%. Experiments at the 90-nm technology node show that our methodology can further reduce the peak noise and the Decap requirement by 16.57% and 44.85% with PAO, or 18.16% and 47.58% with DFS. We also show that our approach does not increase the clock period for 0.18-μm technology and beyond. 0.18 micron. 90 micron. Current surge minimization. Decoupling capacitance. Dynamic functional unit selection. Floorplan. High performance clock gated microprocessors. Instructions per cycle. Integrated architectural planning approach. Issue pattern management. Peak noise. Priority assignment optimization. Submodule design. IEEE Transactions on VLSI systems 13, 1 (2005). FO UPD DENG-II Article