Yiran Chen. Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Transactions on VLSI systems.
Citação norma ChicagoYiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems .
Citação norma MLAYiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems, .
Nota: a formatação da citação pode não corresponder 100% ao definido pela respectiva norma.