Cita APA (7a ed.)

Yiran Chen. Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Transactions on VLSI systems.

Cita Chicago Style (17a ed.)

Yiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems .

Cita MLA (9a ed.)

Yiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems, .