Yiran Chen. Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Transactions on VLSI systems.
Chicago-Zitierstil (17. Ausg.)Yiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems .
MLA-Zitierstil (9. Ausg.)Yiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems, .
Achtung: Diese Zitate sind unter Umständen nicht zu 100% korrekt.