Yiran Chen. Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Transactions on VLSI systems.
Citace podle Chicago (17th ed.)Yiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems .
Citace podle MLA (9th ed.)Yiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems, .
Upozornění: Tyto citace jsou generovány automaticky. Nemusí být zcela správně podle citačních pravidel..