APA (7 ম সংস্করণ) উদ্ধৃতি

Yiran Chen. Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Transactions on VLSI systems.

শিকাগো স্টাইল (17 তম সংস্করণ) উদ্ধৃতি

Yiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems .

M.L.A (9 ম সংস্করণ) উদ্ধৃতি

Yiran Chen. "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors." IEEE Transactions on VLSI Systems, .