A process-tolerant cache architecture for improved yield in nanoscale technologies. - Agarwal, A.
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM. Consequently, a large number of cells in a memory are expected to be faulty due to variations in different process parameters. We analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process-tolerant cache architecture suitable for high-performance memory. This technique dynamically detects and replaces faulty cells by dynamically resizing the cache. It surpasses all the contemporary fault tolerant schemes such as row/column redundancy and error-correcting code (ECC) in handling failures due to process variation. Experimental results on a 64-K direct map L1 cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in a 45-nm predictive technology under σVt-inter=σVt-intra=30 mV.
Keywords: 30 mV; 45 nm; 45-nm predictive technology; 50 nm; 64 K; 64-K direct map L1 cache; SRAM cell failure mechanisms; Cache resizing; Contemporary fault tolerant method; Error correcting code; Failure mechanisms; Faulty cell detection; Faulty cell replacing; High performance memory; Minimum geometry transistors; Nanoscale technologies; Process parameter variations; Process-tolerant cache architecture; Row-column redundancy; Sub-50-nm technology regime