Execution cache-based microarchitecture for power-efficient superscalar processors.

Execution cache-based microarchitecture for power-efficient superscalar processors.

This paper investigates a possible solution to the problem of power consumption in superscalar, out-of-order processors by proposing a new microarchitecture, specifically designed to reduce increasing power requirements of high-end processors. More precisely, we show that by modifying the well-estab...

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Detalles Bibliográficos
Publicado en:IEEE Transactions on VLSI systems 13, 1 (2005).
Autor principal: Talpes, E.
Formato: Artículo
Lenguaje:English
Materias:
SPEC2000 benchmarks.
SPEC95 benchmarks.
Average performance loss.
Cache-based microarchitecture.
Dynamic optimizations.
Energy-delay product.
High end processors.
Out-of-order pipeline.
Out-of-order processors.
Out-of-order scheduling.
Power consumption.
Power-efficient superscalar processors.
Processor structure.
Register renaming.
Superscalar processor architecture.