Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder.

Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder.

This paper demonstrates how IEEE 754 floating-point standard compliant rounding can be merged with carry-propagate addition in floating-point unit (FPU) designs by using a novel adaptation of the prefix adder. The paper considers add/subtract, multiply, and SRT divide operations and demonstrates tha...

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Pubblicato in:IEEE Transactions on VLSI systems 13, 2 (2005).
Autore principale: Burgess, N.
Natura: Articolo
Lingua:English
Soggetti:
IEEE 754 floating-point standard.
IEEE floating point operations.
Addition-subtraction operation.
Carry propagate addition.
Contemporary pipelined floating point unit design.
Critical path analysis.
Divide operations.
Flagged prefix adder.
Generic rounding architecture.
Multiply operation.
Prenormalization rounding.
Rounding modes.