A 10-Gb/s CMU

A 10-Gb/s CMU

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-...

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Pubblicato in:IEEE Transactions on VLSI systems 13, 2 (2005).
Autore principale: Centurelli, F.
Natura: Articolo
Lingua:English
Soggetti:
10 Gbit/s.
2.5 V.
20 mV.
3.3 V.
480 mW.
780 mW.
PLL.
SDH-SONET.
SiGe.
SiGe BiCMOS commercial technology.
Charge pump.
Clock multiplier unit-clock-data recovery chip set.
Clock phase margin.
Decision circuit.
Dual loop phase locked loop.
Dual reference clock frequency.
Frequency ripple minimization.
Jitter minimization.
Multistandard compliance.
Phase detector topology.
Phase tracking loop.
Power consumption.
Sensitivity limiting amplifier.
Transition density factor.