Low-power scan design using first-level supply gating.

Low-power scan design using first-level supply gating.

Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In th...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 13, 3 (2005).
Päätekijä: Bhunia, S.
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
ISCAS89 benchmark.
Battery lifetime.
Combinational logic.
Fault simulation.
First level supply gating.
Flip-flops.
Leakage power reduction.
Low power scan design.
Masking effect.
Portable electronic devices.
Power dissipation.
Reliability.
Scan based testing.
Signal transition.
Supply gating transistor.
Test cost reduction.
Test power reduction.
Vector control.