Bhunia, S. Low-power scan design using first-level supply gating. IEEE Transactions on VLSI systems.
Chicago Style (17th ed.) CitationBhunia, S. "Low-power Scan Design Using First-level Supply Gating." IEEE Transactions on VLSI Systems .
MLA (9th ed.) CitationBhunia, S. "Low-power Scan Design Using First-level Supply Gating." IEEE Transactions on VLSI Systems, .
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