A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations.

A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations.

This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache l...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 13, 3 (2005).
Main Author: Kim, C.H
Format: Article
Language:English
Subjects:
CMOS technology.
SRAM cache memories.
SRAM cells.
Combined device-circuit-architecture level techniques.
Device-circuit-architecture level technique.
Forward body biasing technique.
Leakage power reduction.
Nanoscale leakage mechanism.
Static noise margin.
Threshold voltage devices.
Transition latency.
Two dimensional halo doping profile.