APA (7th ed.) Citation

Kim, C. A forward body-biased low-leakage SRAM cache: Device, circuit and architecture considerations. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Kim, C.H. "A Forward Body-biased Low-leakage SRAM Cache: Device, Circuit and Architecture Considerations." IEEE Transactions on VLSI Systems .

MLA (9th ed.) Citation

Kim, C.H. "A Forward Body-biased Low-leakage SRAM Cache: Device, Circuit and Architecture Considerations." IEEE Transactions on VLSI Systems, .