Optimization of throughput performance for low-power VLSI interconnects.

Optimization of throughput performance for low-power VLSI interconnects.

The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bit-rate of a very large scale integration interconnect with repeaters has been derived and results are compared with HSP...

Ausführliche Beschreibung

Bibliographische Detailangaben
Veröffentlicht in:IEEE Transactions on VLSI systems 13, 3 (2005).
1. Verfasser: Deodhar, V.V
Format: Artikel
Sprache:English
Schlagworte:
1 V.
180 nm.
2 V.
Low power VLSI interconnects.
Low power global interconnect.
Microoptical silicon system technology.
Optimal supply voltage.
Optimal voltage scaling.
Optimization.
Power dissipation.
Repeater insertion.
Threshold voltage.
Throughput-per-bit-energy.
Very large scale integration.