POMR a power-aware interconnect optimization methodology.

As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, un...

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Xuất bản năm:IEEE Transactions on VLSI systems 13, 3 (2005).
Tác giả chính: Youssef, A.
Định dạng: Bài viết
Ngôn ngữ:English
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