POMR a power-aware interconnect optimization methodology.

POMR a power-aware interconnect optimization methodology.

As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, un...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 13, 3 (2005).
Main Author: Youssef, A.
Format: Article
Language:English
Subjects:
MCNC benchmark circuits.
MOS integrated circuits.
POMR.
VLSI technology.
Buffer insertion problem.
Buffer sizing problem.
Chip power consumption.
Dual threshold buffers.
Global interconnect buffers.
Integrated circuit testing.
Optimal power maze routing.
Power aware interconnect optimization.
Power saving.
Pseudopolynomial time bound.
Shortest path ranking problem.