00000cab a22000003a 4500 UP-99796217609611386 Buklod 20231007234430.0 m |o d | ta 110112s xx d | ||r ||||| || DENGII eng Chang Hoon Kim A digit-serial multiplier for finite field GF(2m). pp. 476-483 In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2m) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data come in continuously, the proposed array can produce multiplication results at a rate of one every ┌m/L┐ clock cycles, where L is the selected digit size. Analysis shows that the computational delay time of the proposed architecture is significantly less than the previously proposed digit-serial systolic multiplier. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation. VLSI implementation. Computational delay time. Dependence graph. Digit-serial multiplier. Finite field multiplication. Least significant bit first multiplication algorithm. Systolic array. Unidirectional data flow. IEEE Transactions on VLSI systems 13, 4 (2005). FO UPD DENG-II Article