Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication.

This paper demonstrates the design of efficient asynchronous bundled-data pipelines for the matrix-vector multiplication core of discrete cosine transforms (DCTs). The architecture is optimized for both zero and small-valued data, typical in DCT applications, yielding both high average performance a...

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書誌詳細

出版年:	IEEE Transactions on VLSI systems 13, 4 (2005).
第一著者:	Tugsinavisut, S.
フォーマット:	論文
言語:	English
主題:	Asynchronous bundled-data pipelines. Asynchronous design. Asynchronous pipelines. Control-circuit template. Data-dependent delay lines. Discrete cosine transforms. Energy overhead. Four-phase full buffer. Integrated control circuitry. Matrix-vector multiplication. Nonlinear pipelines. Speculative completion sensing. Timing analysis.