00000cab a22000003a 4500 UP-99796217609611379 Buklod 20231007234430.0 m |o d | ta 110112s xx d | ||r ||||| || DENGII eng Dobkin, R. Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. pp. 427-438 Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area. VLSI implementations. Coding gain. Error correction performance. Latency reduction. Low-latency MAP turbo decoders. Maximum a posteriori algorithm. Multiple single-input single-output. Parallel VLSI architecture. Parallel interleaver. Sequential architectures. IEEE Transactions on VLSI systems 13, 4 (2005). FO UPD DENG-II Article