Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.

Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one t...

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Detalles Bibliográficos
Publicado en:IEEE Transactions on VLSI systems 13, 4 (2005).
Autor Principal: Dobkin, R.
Formato: Artigo
Idioma:English
Subjects:
VLSI implementations.
Coding gain.
Error correction performance.
Latency reduction.
Low-latency MAP turbo decoders.
Maximum a posteriori algorithm.
Multiple single-input single-output.
Parallel VLSI architecture.
Parallel interleaver.
Sequential architectures.