APA (7th ed.) Citation

Dobkin, R. Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Dobkin, R. "Parallel Interleaver Design and VLSI Architecture for Low-latency MAP Turbo Decoders." IEEE Transactions on VLSI Systems .

MLA (9th ed.) Citation

Dobkin, R. "Parallel Interleaver Design and VLSI Architecture for Low-latency MAP Turbo Decoders." IEEE Transactions on VLSI Systems, .