00000cab a22000003a 4500 UP-99796217609611378 Buklod 20231007234430.0 m |o d | ta 110112s xx d | ||r ||||| || DENGII eng Xinmiao Zhang Fast factorization architecture in soft-decision Reed-Solomon decoding. pp. 413-426 Reed-Solomon (RS) codes are among the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to its hard-decision counterpart, soft-decision decoding offers considerably higher error-correcting capability. The recent development of soft-decision RS decoding algorithms makes their hardware implementations feasible. Among these algorithms, the Koetter-Vardy (KV) algorithm can achieve substantial coding gain for high-rate RS codes, while maintaining a polynomial complexity with respect to the code length. In the KV algorithm, the factorization step can consume a major part of the decoding latency. A novel architecture based on root-order prediction is proposed in this paper to speed up the factorization step. As a result, the time-consuming exhaustive-search-based root computation in each iteration level, except the first one, of the factorization step is circumvented with more than 99% probability. Using the proposed architecture, a speedup of 141% can be achieved over prior efforts for a (255, 239) RS code, while the area consumption is reduced to 31.4%. Chien search. Guruswami-Sudan algorithm. Koetter-Vardy algorithm. Reed-Solomon codes. VLSI architecture. Code length. Coding gain. Computer systems. Decoding latency. Error-correcting codes. Factorization step. Fast factorization architecture. Hardware implementations. High-rate RS codes. Modern communication. Polynomial complexity. Root-order prediction. Soft-decision Reed-Solomon decoding. IEEE Transactions on VLSI systems 13, 4 (2005). FO UPD DENG-II Article