A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.

This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated d...

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书目详细资料
发表在:IEEE Transactions on VLSI systems 13, 5 (2005).
主要作者: Olivieri, M.
格式: 文件
语言:English
主题:
CMOS process.
Body bias active control.
Design flow.
Digital CMOS circuits.
Digital integrated circuits yield.
Estimation circuits.
On-chip digital controller.
Process parameters.
Run-time estimation.
Yield optimization.