Power complexity of multiplexer-based optoelectronic crossbar switches. - Szymanski, T.H.
The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no sufficiently general analytic methodology for power analysis and power reduction of large-scale crossbar switching systems. An analysis of the power complexity of single-chip optoelectronic switches is presented, assuming the classic broadcast-and-select crossbar architecture. The analysis yields the distribution of power dissipation and allows for design optimization. Both unpipelined and pipelined designs are analyzed, and a technique to reduce power dissipation significantly is proposed. The design of a 5.12 Tbit single-chip optoelectronic switch using 0.18-μm CMOS technology is illustrated. The pipelined switch design occupies < 70 mm2 of CMOS area, and consumes <80 W of power, which compares favorably to the power required in electrical crossbar switches of equivalent capacity.
Keywords: 0.18 micron; CMOS technology; VLSI; Broadcast-and-select crossbar; Design optimization; Electronic crossbar switching; Multiplexer-based optoelectronic crossbar switches; Optical input/output devices; Optoelectronic integrated circuit; Optoelectronic switches; Pipelined switch design; Power analysis; Power complexity; Power dissipation; Power reduction